Among liquid crystal display devices, some liquid crystal display devices include a liquid crystal panel where a display section and a peripheral circuit such as a driver circuit are fabricated on a single substrate. The liquid crystal display devices each including such a liquid crystal panel is capable of achieving simplification of a panel mounting process, reduction in mounting area which reduction leads to a narrower frame, a smaller size, and a smaller weight, and the like, as compared to conventional liquid crystal display devices for each of which an IC for realizing a peripheral circuit is provided externally but not on a glass substrate.
Examples of the peripheral circuit encompass a buffer circuit, a level shifter circuit, and the like in addition to driver circuits such as a gate driver, a CS driver and a source driver. These peripheral circuits each are configured by a semiconductor circuit (semiconductor device) including a transistor, and the like.
The transistor here has a predetermined threshold voltage. Accordingly, a potential level of an output signal of the transistor decreases due to voltage drop that is caused by the threshold voltage of the transistor itself. On this account, when a circuit configuration is designed, it has been required to take the threshold voltage into consideration for obtaining an output at a desired potential level from the transistor. The peripheral circuit is required to provide an output at a predetermined potential level, so as to cause a circuit in a subsequent stage to stably operate without malfunctioning and so as to normally and sequentially drive pixels disposed in a display section.
In view of this, a technique called a bootstrap operation is proposed (See Patent Literatures 1 and 2, for example). In the bootstrap operation, a potential level of a signal is increased (pumped up) so that the signal satisfies a sufficient potential level.
The following discusses the bootstrap operation with reference to a semiconductor device described in Patent Literature 2.
FIG. 6 is a circuit diagram illustrating a configuration of a semiconductor device 1 described in Patent Literature 2. As illustrated in FIG. 6, the semiconductor device 1 includes a transistor Ta1, a transistor Ta2, a transistor Ta3, a transistor Ta4, a transistor Ta5, a transistor Tb1, a transistor Tb2, a transistor Tb3, a transistor Tb4, a transistor Tb5, a capacitor Ca1, and a capacitor Cb1. All the transistors are n-channel type MOS transistors. The semiconductor device 1 is configured as a memory circuit including transistors of an identical power supply type.
Further, the semiconductor device 1 is configured so that the semiconductor device 1 can be connected to a power supply VDD and a power supply VSS. In this configuration, for example, the power supply VDD has a positive potential, while the power supply VSS is GND. However, the configuration of the semiconductor device 1 is not limited to this configuration.
Further, the semiconductor device 1 is configured to receive input of an input signal IN, an inversion input signal INB (an inversion signal of the input signal IN), a clock signal CK, and an enable signal EN and to output an output signal OUT and an inversion output signal OUTB (an inversion signal of the output signal OUT). The input signal IN, the inversion input signal INB, the clock signal CK, the enable signal EN, the output signal OUT, and the inversion output signal OUTB become a high level when active. Meanwhile, these signals become a low level when inactive. The following assumes that (i) at the high level, these signals each have a potential equal to a potential of the power supply VDD and (ii) at the low level, these signals each have a potential equal to a potential of the power supply VSS.
Note that because the input signal IN, the inversion input signal INB, the clock signal CK, the enable signal EN, the output signal OUT, and the inversion output signal OUTB are input signals each inputted via a terminal (electrode) or output signals each outputted via a terminal (electrode), for convenience of explanation, hereinafter, the input signal IN is also referred to as an input terminal IN, the inversion input signal INB as an inversion input terminal INB, the clock signal CK as a clock terminal CK, the enable signal EN as an enable terminal EN, the output signal OUT as an output terminal OUT, and the inversion output signal OUTB as an inversion output terminal OUTB.
The transistor Ta1 is configured such that a drain terminal of the transistor Ta1 is connected to the power supply VDD, and a gate terminal of the transistor Ta1 is connected to a source terminal of the transistor Ta5 and the output terminal OUT. Further, a source terminal of the transistor Ta1 is connected to a gate terminal of the transistor Ta2 and a drain terminal of the transistor Ta3, and also connected to the clock terminal CK via the capacitor Ca1. The transistor Ta2 is configured such that a drain terminal of the transistor Ta2 is connected to the power supply VDD, and a source terminal of the transistor Ta2 is connected to a drain terminal of the transistor Ta4 and the output terminal OUT. The transistor Ta3 is configured such that a gate terminal of the transistor Ta3 is connected to the inversion output terminal OUTB and a source terminal of the transistor Ta3 is connected to the power supply VSS. The transistor Ta4 is configured such that a gate terminal of the transistor Ta4 is connected to the inversion output terminal OUTB and a source terminal of the transistor Ta4 is connected to the power supply VSS. The transistor Ta5 is configured such that a drain terminal of the transistor Ta5 is connected to the input terminal IN and a gate terminal of the transistor Ta5 is connected to the enable terminal EN.
The transistor Tb1 is configured such that a drain terminal of the transistor Tb1 is connected to the power supply VDD, and a gate terminal of the transistor Tb1 is connected to a source terminal of the transistor Tb5 and the inversion output terminal OUTB. Further, a source terminal of the transistor Tb1 is connected to a gate terminal of the transistor Tb2 and a drain terminal of the transistor Tb3, and also connected to the clock terminal CK via the capacitor Cb1. The transistor Tb2 is configured such that a drain terminal of the transistor Tb2 is connected to the power supply VDD, and a source terminal of the transistor Tb2 is connected to a drain terminal of the transistor Tb4 and the inversion output terminal OUTB. The transistor Tb3 is configured such that a gate terminal of the transistor Tb3 is connected to the output terminal OUT, and a source terminal of the transistor Tb3 is connected to the power supply VSS. The transistor Tb4 is configured such that a gate terminal of the transistor Tb4 is connected to the output terminal OUT and a source terminal of the transistor Tb4 is connected to the power supply VSS. The transistor Tb5 is configured such that a drain terminal of the transistor Tb5 is connected to the inversion input terminal INB, and a gate terminal of the transistor Tb5 is connected to the enable terminal EN.
Note that a joint between the capacitor Ca1 and each of the transistors Ta1, Ta2, and Ta3 is referred to as a node na1. Meanwhile, a joint between the capacitor Cb1 and each of the transistors Tb1, Tb2, and Tb3 is referred to as a node nb1.
Next, the following explains an operation of the semiconductor device 1 that is configured as described above.
FIG. 7 is a timing chart illustrating respective wave forms of various signals in the semiconductor device 1. Here, the explanation is given on a case where, after a period A in which a high-level (VDD) output signal OUT is outputted and a low-level (VSS) inversion output signal OUTB is outputted, the period A shifts to a period B in which a low-level output signal OUT is outputted and a high-level inversion output signal OUTB is outputted.
(Period A)
In the semiconductor device 1 into which the clock signal CK is inputted, the input signal IN becomes a high level and the inversion input signal INB becomes a low level. Subsequently, when the enable signal EN becomes a high level, the transistors Ta5 and Tb5 are turned ON. The clock signal CK shows a wave form that periodically repeats the high level and the low level. The clock signal CK is inputted at a frequency that is higher than respective frequencies of the output signal OUT and the inversion output signal OUTB.
At this time, because the transistor Ta5 is ON and the input signal IN is at a high level, the transistor Ta1 is turned ON. This causes a potential of the node na1 to be VDD−Vth (precharge operation), where a threshold voltage of the transistor Ta1 is Vth. When the potential of the node na1 increases, the transistor Ta2 is turned ON.
Then, when the enable signal EN shifts from a high level to a low level, the transistor Ta5 and the transistor Ta1 are turned OFF. As a result, the node na1 becomes a floating state while keeping a high charge. In this state, when the clock signal CK becomes a high level, the potential of the node na1 is pumped up by a potential of a due to the clock signal CK so as to become Vdd−Vth+α. When this potential of the node na1 is higher than VDD+Vth, the transistor Ta2 outputs VDD to the output terminal OUT.
When the potential of the node na1 is pumped up due to clock signal CK as described above, a high-potential signal is inputted into the gate terminal of the transistor Ta2. Accordingly, a signal at a VDD potential level, that is, a signal that has not suffered threshold drop is outputted from the transistor Ta2 to the output terminal OUT.
Note that after the enable signal EN once becomes a high level, a high-level signal can be consistently inputted into the gate terminal of the transistor Ta1 as long as the output signal OUT is at a high level. Even when the enable signal EN becomes a low level, the high-level signal can be inputted as long as the output signal OUT is at a high level. This makes it possible to keep a high-level output signal OUT.
Further, the output terminal OUT and the gate terminal of the transistor Ta1 are connected to each other. Accordingly, while the high-level output signal OUT is being outputted, the transistor Ta1 is turned ON when the potential of the node na1 becomes Vdd−Vth or lower. Note that when the potential of the node na1 is Vdd−Vth or higher, the transistor Ta1 is turned OFF and the node na1 becomes a floating state.
Consequently, while the high-level output signal OUT is being outputted, the potential of the node na1 is recharged to Vdd−Vth (refresh operation) by the transistor Ta1 even when the potential of the node na1 decreases due to off leakage or the like. This makes it possible to pump up the potential of the node na1 to Vdd−Vth+α while a high-level clock signal CK is being outputted. Therefore, a VDD output signal OUT can be stably outputted.
Meanwhile, while the high-level output signal OUT is being outputted, the transistors Tb3 and Tb4 are turned ON. As a result, an electric charge of the node nb1 is discharged and the inversion output signal OUTB becomes a low level.
(Period B)
Next, when the input signal IN becomes a low level and the inversion input signal INB becomes a high level and subsequently, the enable signal EN becomes a high level, the transistors Ta5 and Tb5 are turned ON.
At this time, because the transistor Tb5 is ON and the inversion input signal INB is at a high level, the transistor Tb1 is turned ON. This subsequently causes a potential of the node nb1 to be Vdd−Vth (precharge operation), where Vth is a threshold voltage of the transistor Tb1. When the potential of the node nb1 increases, the transistor Tb2 is turned ON.
Then, when the enable signal EN shifts from a high level to a low level, the transistors Tb5 and Tb1 are turned OFF. Further, the node nb1 becomes a floating state while keeping a high charge. In this state, when the clock signal CK becomes a high level, the potential of the node nb1 is pumped up by a potential of a due to the clock signal CK and becomes VDD−Vth+α. When this potential of the node nb1 is higher than VDD+Vth, the transistor Tb2 outputs VDD to the inversion output terminal OUTB.
When the potential of the node nb1 is pumped up due to the clock signal CK as described above, a high-potential signal is inputted into the gate terminal of the transistor Tb2. Accordingly, a signal at a VDD potential level, that is, a signal that has not suffered threshold drop is outputted from the transistor Tb2 to the inversion output terminal OUTB.
Note that in the same manner as described above, after the enable signal EN once becomes a high level, a high-level signal can be consistently inputted into the gate terminal of the transistor Tb1 as long as the inversion output terminal OUTB is at a high-level. Even when the enable signal EN becomes a low level, the high-level signal can be inputted as long as the inversion output terminal OUTB is at a high-level. This makes it possible to keep a high-level inversion output signal OUTB.
Further, while the high-level inversion output signal OUTB is being outputted, the potential of the node nb1 is recharged to Vdd−Vth (refresh operation) by the transistor Tb1 even when the potential of the node nb1 decreases due to off leakage or the like. This makes it possible to pump up the potential of the node nb1 to Vdd−Vth+α while a high-level clock signal CK is being outputted. Therefore, a VDD inversion output signal OUTB can be stably outputted.
Meanwhile, while the high-level inversion output signal OUTB is being outputted, the transistor Ta3 and Ta4 are turned ON. As a result, an electric charge of the node na1 is discharged and the output signal OUT becomes a low level.
As described above, in the period A, the high-level output signal OUT and a low-level inversion output signal OUTB are outputted, while in period B, a low-level output signal OUT and the high-level inversion output signal OUTB are outputted. In accordance with a timing at which the enable signal EN becomes a high level, the periods A and B are switched. When one of the output signal OUT and the inversion output signal OUTB outputted is a VDD signal, the other one of the output signal OUT and the inversion output signal OUTB outputted is a VSS signal.
Note that an amplitude of the clock signal CK, and a capacitance Ca1 and a capacitance Cb1 are set so that respective pumped-up potentials (Vdd−Vth+α) of the nodes na1 and nb1 become VDD+Vth or higher.
As described above, in the semiconductor device 1, a frequency of the clock signal CK is set so as to be higher than a frequency of each of the output signal OUT and the inversion output signal OUTB. Therefore, even when respective potentials of the nodes na1 and nb1 decrease due to off leakage or the like, it is possible to pump up the respective potentials of the nodes na1 and nb1 to VDD+Vth or higher by a pump-up operation caused by the clock signal CK before the enable signal EN becomes a high level next time. That is, the semiconductor device 1 is configured such that respective potential levels of the nodes na1 and nb1 are increased by a bootstrap operation so as to satisfy a sufficient potential level.
Accordingly, it becomes possible to stably output VDD from the output terminal OUT and the inversion output terminal OUTB. This makes it possible to obtain a stable operation in a circuit of a subsequent stage that is connected to the output terminal OUT and the inversion output terminal OUTB.